Complex Instruction Set Computer
(CISC) A processor where each instruction can perform several
low-level operations such as memory access, arithmetic
operations or address calculations. The term was coined in
contrast to {Reduced Instruction Set Computer}.
Before the first RISC processors were designed, many computer
architects were trying to bridge the "{semantic gap}" - to
design {instruction set}s to support {high-level language}s by
providing "high-level" instructions such as procedure call and
return, loop instructions such as "decrement and branch if
non-zero" and complex {addressing mode}s to allow data
structure and {array} accesses to be compiled into single
instructions.
While these architectures achieved their aim of allowing
high-level language constructs to be expressed in fewer
instructions, it was observed that they did not always result
in improved performance. For example, on one processor it was
discovered that it was possible to improve the performance by
NOT using the procedure call instruction but using a sequence
of simpler instructions instead. Furthermore, the more
complex the instruction set, the greater the overhead of
decoding an instruction, both in execution time and silicon
area. This is particularly true for processors which used
{microcode} to decode the (macro) instruction. It is easier
to debug a complex instruction set implemented in microcode
than one whose decoding is "{hard-wired}" in silicon.
Examples of CISC processors are the {Motorola} {680x0} family
and the {Intel 80186} through {Intel 486} and {Pentium}.
(1994-10-10)